`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:26:10 01/12/2011 
// Design Name: 
// Module Name:    reg_file 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

// Parameters:
// 	WIDTH -> Width of the data stored in each register
//	LOG_NUM_REGS -> Log-base-2 of the number of registers (number of bits needed to specify a register)
module reg_file#(parameter WIDTH = 8, LOG_NUM_REGS = 2)
(
	// Global clock
	input clk,
	// Global reset
	input reset,
	
	// Encoded register inputs
	input [LOG_NUM_REGS - 1 : 0] r1_in,
	input [LOG_NUM_REGS - 1 : 0] r2_in,
	
	// Data to be written on the next clock cycle
	input [WIDTH - 1 : 0] r_data_in,
	// Should we write this cycle?
	input regfile_write_en_in,

	// The asynchronous outputs for register reads (indexed via the inputs)
	output [WIDTH - 1 : 0] v1_out,
	output [WIDTH - 1 : 0] v2_out
);

reg [WIDTH-1:0] reg0;
reg [WIDTH-1:0] reg1;
reg [WIDTH-1:0] reg2;
reg [WIDTH-1:0] reg3;

assign v1_out = ( r1_in == 0 ) ? reg0 : 
					 ( r1_in == 1 ) ? reg1 : 
					 ( r1_in == 2 ) ? reg2 : 
					 ( r1_in == 3 ) ? reg3 : 0;
					 
assign v2_out = ( r2_in == 0 ) ? reg0 : 
					 ( r2_in == 1 ) ? reg1 : 
					 ( r2_in == 2 ) ? reg2 : 
					 ( r2_in == 3 ) ? reg3 : 0;
			
always@(*)
	begin
		if (reset == 1)
			begin
				reg0 <= 0;
				reg1 <= 0;
				reg2 <= 0;
				reg3 <= 0;
			end
	end
	
always@(posedge clk)
	begin 
		if (regfile_write_en_in == 1)
		case(r1_in)
			0:	reg0 <= r_data_in;
			1: reg1 <= r_data_in;
			2: reg2 <= r_data_in;
			3: reg3 <= r_data_in;
		endcase
	end 
	
endmodule 